A Pipelined Splittable Multiply-accumulate Unit Architecture
Dongxiao Li · Jisuanji gongcheng · 2006
A pipelined splittable multiply-accumulate unit architecture designed for media digital signal processor is presented in this paper.The MAC operations are pipelined to achieve single-cycle 32-bit × 32-bit MAC throughput at 200 MHz.Splittable data-path architecture is employed to support 4-way 16-bit × 16-bit single-instruction-multiple-data(SIMD) MAC instructions.The MAC architecture is physically verified in silicon DSP chip.