Low Power High Throughput FIR Filter Design with Distributed Arithmetic Implemention
Gaoping Shao · Jisuanji yingyong yanjiu · 2006
Based on the design ideology of SoC,a technique for low power high throughput realization of Finite Impulse Response(FIR) filters implemented using Distributed Arithmetic is presented.In most applications,the coefficient of filter is constant,it can use DA constructure to realize the filter,the distribution profile of input data values is known,the proposed technique uses a data encoding which can be tuned to the specific distribution profile so as to reduce switch.This paper uses Nega Binary coding approach for input data pre-coding to reduce the arithmetic activity,combines the column shift register with gray coded addressing to minimize the power dissipated in data shifting and addressing bus,appends pipline strurally to receive improvement in high throughput.At the end of,it presents the realization of FPGA.