Research on the Formal Semantics of Verilog Based on ASM
Yanxiang Hu · Jisuanji gongcheng · 2006
Verilog’s formal semantics using the abstract states machine are studied,and the formal definition of assignment statements and delay/event control mechanism is given.Comparing with Borger’s definition on VHDL,the key methods on how to translate Verilog description to VHDL are explained.In the end,the simulation differences before and after translation are studied.