The Design of a Bus Monitor
Yang Yu · Microelectronics & Computer · 2004
As the grows of the VLSI design scale, traditional verification methods can not satisfy the SoC verification request, because it dose not supply the enough ability to check all the function rightness and can not ensure the product quality. Verification reuse methodology can solve this problem effective. In SoC verification, we can make use of bus protocol checker to monitor bus, and monitored result display in a special format, so we can estimate the validity of bus data, and check models and the system. This paper advances the design method of bus monitor in SoC and presents the material implementation.