Hardware Implementation of Configurable High-speed and High-precision FFT
Xiaofeng Tang · Jisuanji gongcheng · 2006
A novel method is proposes to design a configurable,mixed-Radix8/4/2 and floating-point high-speed FFT processor.The improved mixed-Radix8/4/2 algorithm,ping-pong RAM architecture,data address generator and pipelining floating-point process unit which enhance the processor's performance to read,write,compute 16 data simultaneously and process unfixed point with high-precision are discussed in detail.The design has been verified on the FPGA platform and synthesized in 0.18μm CMOS technology.It is showed that the IO rate is 250MSPS at 4k point and will reach to 800MSPS after its migration to ASIC.