Physical design of 128-point FFT processor applied in UWB system
Yang Zun-xian · Fuzhou daxue xuebao. Ziran kexue ban · 2011
After logic synthesis and DFT design,the physical design of 128-point FFT processor applied in UWB system is introduced.Based on SMIC 0.18 μm CMOS technology,the back-end design flow includes floorplan,powerplan,placement,clock tree synthesis,static timing analysis and optimization using SoC Encounter 5.2.After nano route,the physical verification including DRC(design rule check) and LVS(layout versus schematic) and formality are carried on.The clock frequency of this FFT chip is 76.9 MHz,and the chip area is about 6.5 mm2.