DPWM with High Resolution and Low Power Consumption Based on FPGA
Lei Luo · Video Engineering · 2012
A design scheme of Digital Pulsewidth Modulator(DPWM)based on FPGA with low power consumption and high resolution is presented.This scheme realizes high resolution DPWM and reduces requirement of system clock frequency at the same time.The method fully utilizes frequency duplication and phase shift functions of Digital Clock Managers(DCM),and makes DCM block just work at 1/16 of the switch cycle,and then decreases power dissipation.This paper achieves DPWM of 11 bit resolution and passes the simulation and verification conducted in FPGA in the case that the system clock frequency is 16 MHz and the switch frequency is 1 MHz.