A Generic BIST Builder of Multiple RAM Modules Embedded in ASIC Chips
Jong-Kwon Chang · The Transactions of the Korea Information Processing Society · 1998
In this paper we propose a generic BIST builder for the Embedded Multiple HAM modules in ASICs, The BlST circuitry is automatically generated according to the specification of the target RAM Modules and the applying test algorithms to them. The lJIST is designed using the TOP-DOWN technique and, thus, has the several advantages in the area of the selection of test algorithm, the development of the circuitry, and the reuse of the circuitry, In addition, we have modified the existing serial interiacing approach to obtain smaller additional BlST circuitry and higher fault coverage and better B1ST sharing of the target RAM Modules in ASICs,