The Design of Monitor for Verification Reuse
Wenfa Zhan · Microelectronics & Computer · 2004
Modern IC design is faced with a dilemma. On the one hand, ASIC and SoC designs are getting more complex; on the other hand, the pressure from TTM is increased. Generally, verification process consumes over 70 percent of the design team's work. Decreasing verification time make design efficiency increased. Verification reuse methodology is a viable technique to decrease verification time. Transaction-based monitor is an important composition of reusable verification environment. This paper introduce the related theory and the design method of a monitor, then a real-world example ,bus monitor, is also proposed.