FPGA implementation of a high-speed base-2 256-point FFT
Weiping Jing · Journal of Circuits and Systems · 2005
This paper provides the design method of a high speed based 2 FFT processor using FPGA and ASIC. It employs radix-2 DIT arithmetic and fixed point core. A structure of anti-overflow which enhances computing precision without reducing the performance has been designed. A symmetry ping-pang structure has been brought forward to increase the continuous computing capability of the butterfly core. In order to promoting its flexibility, the RAMs have been integrated with the FFT processor. The number of processing points is configurable, which is 2n. 1072 clock periods are needed to achieve a 256 point FFT computation. The processor has been realized with VertexII-xc2v1000256-4 which shows that the frequency can reach 112.007MHz, and computing time is 9.57μs.