Design of test pattern generator based on pseu-SIC test sequence
Tang Lan · Shenyang Gongye Daxue xuebao · 2008
In order to reduce the power consumption in BIST, a new BIST TPG design that can highly reduce the test power consumption without losing fixed fault coverage has been proposed through analyzing the general low power design methods and in view of enhancing the relativity between test vectors.By adding simple control logic circuit on the original LFSR,the designed generator can generate a new pseu-SIC(single input change) test sequence.The experimental results conducted on benchmark circuit show that the proposed design can greatly reduce test time and power consumption.