Low Peak Power Consumption BIST Scheduling Algorithm for SoC
Yang Jun, Asic System · Journal of Circuits and Systems · 2004
A low peak power consumption Built-in self-test (BIST) scheduling algorithm for system-on-a-chip (SoC) is presented. First a compact power model of scan based BIST is proposed. Based on the model, excessive peak power consumption during test can be avoided by adjusting the BIST period and controlling each BISTs startup. Experiment shows that peak power during concurrent BIST execution can be by reduced by the proposed scheduling algorithm.