Design of a Decoder Circuit with Hybrid Architectures of SET and MOS Transistors
Wu Gang · Microelectronics & Computer · 2008
Based on the I-V characteristics of single-electron transistor and the idea of MOS digital logic circuits,an inverter using the hybrid SET/MOS transistors was proposed and the NOR gate was expanded.Finally,a novel uniquely address decoder was realized using these logic circuits,which,compared with the pure SET circuit,is considerably augmented in its drive capability,compared with the MOS circuit,it needs likewise one resource support the power,but the number of transistor is decreased and the total static power depletion is reduced.The accuracy of the circuit is validated by SPICE.