Optimization of Explicit Redundancy in Gate-Level Technology Mapping
Wang Zuo · Journal of Computer-Aided Design & Computer Graphics · 2001
Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping.Explicit redundancy can not improve the performance,but increases power consumption,enlarges circuit area and decreases its testability,so it should be removed.This paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability.