Design and FPGA Realization of High Code-rate Adaptive Turbo Encoder and Decoder
Huang Yi · Telecommunication Engineering · 2008
A new FPGA realization scheme for high code-rate adaptive Turbo encoder/decoder is proposed.In encoding module,the block helix symmetric interleaver with specific parameters was used to construct high code-rate by puncturing and insure termination of both encoders by appending the same set of bits.In SOVA decoding module,parallel computation for the cumulative metric values of two candidate paths at each state and parallel update for the reliability values improve the decoding speed.The simulation result shows that the high code-rate adaptive encoder/ decoder has good BER performance and can be put into practical use.