The research of the power consumption of the AES encryption algorithm based on FPGA
Guo Zheng-z · Journal of Hebei University of Technology · 2015
AES(Advanced Encryption Standard) is an Encryption Standard proposed by American national standards institute of technology NIST to replace DES Encryption Standard in the 21 st century. The principle of AES encryption algorithm was introduced in detail; the design and function simulation of the AES encryption algorithm based on FPGA platform were completed. Reducing power consumption of the AES encryption algorithm based on FPGA was discussed.The causes of the power consumption were analysed from static and dynamic aspects. With the increase of clock frequency,the tendency of the system power consumption was studied, too. Algorithm module occupies less logical resources, yet has high efficiency in encryption. The purpose of balancing the two important parameters-data processing speed and power consumption has been reached upon the preconditions of guaranteeing the security and meeting the demand of many applications.