Design and Implementation of High Speed and Fixed-point FFT Processor
Bo Fu · Jisuanji gongcheng · 2005
The paper presents the design method of a high speed and fixed-point FFT processor. By optimizing the memory mapping algorithm and the generation of twiddle factors, the method based on CORDIC algorithm can calculate a radix-4 butterfly in one clock cycle and has the maximal degree of parallelism. This paper also introduces a method of twiddle factor generation, which can simultaneously generate three twiddles of one radix-4 butterfly. The implementation of the twiddle factor generation in hardware is simple and don’t need extra ROM resources. The processor has been implemented on a Xilinx chip XCV2P30 and obtains the operating clock frequency at 130MHz. The processor can compute a complex 1024-point FFT with 9.8μs and 16384-point FFT with 221μs. The performance of the FFT processor is better than most available FFT processors.