An Analog Decoder Realized by CMOS Circuits for(5,2,3) Trellis Code
Shuhui Yang · Signal Processing · 2009
Basing on the a-posterior probability algorithm(APP) and the CMOS technique,the paper fabricates a full analog probability decoder of(5,2,3) trellis code.Some circuits of the decoder are analyzed in detail.The decoding performance is given. When S/N is 4.8dB,for 950KHz input signal,there is no error in the output of the decoder.When the frequency of the input signal is 6MHz,the error bit rate is about 10~(-4).The maximal rate will be 20MHz.Simulation results show that the analog decoder decreases at least one order of magnitude in power consumption and chip area for the same bit rate,compared with the decoder designed by digital circuits.The design method also can be used for implementing the analog decoder of Turbo code and LDPC code.There will be great improvement in the respect to the power consumption and the chip area of the analog decoder.