The Design and Realization of 8k-point FFT Based on FPGA
Ye Jiang · Journal of Jiamusi University · 2009
The paper is about using 4k-point complex FFT to realize 8k-point real FFT,the data storage units adopts double-port Ping-pong RAM and the level coupling structure design mode.A pipeline is employed.The radix 4 butterfly implement forward 6 grades computation and Double Radix 2 butterfly implement the last grades computation.At the same time,the block floating-point overflow was used to test.Experimentation indicates that adopting FFT processor realizes 8K-point real FFT just needs 35,799μs,under the common state that the clock-period is 8.74 ns,this gets the results of high-speed calculation.