Design of Synchronization Accelerator in HPC Computing Node
Nongda Hu · Dianzi Ke-ji Daxue xuebao · 2012
With the widely use of acceleration devices,hardware parallelism of single hybrid programming computer(HPC) node has increased many.As a result,both on-chip communication and inter-node communication become more and more frequently.Apparently,communication is becoming the bottleneck of system performance.This paper proposes a design of hardware module called synchronization accelerator to accelerate synchronization communication patterns.These patterns include fine-grain synchronization,barrier,and all-reduce.At the scale of 16 processes,synchronization accelerator can achieve about 4 times speedup than software-based collective operations.Also,the performance of benchmark LU can achieve 20% improvement with the use of synchronization accelerator.