VLSI Design and Implementation of Fully Pipelined FFT Processor
Zhao Haibin · Journal of Henan University · 2010
A fast and fully pipelined architecture of FFT processor customized for OFDM-based communication systems is presented.For the finite word length effects consideration of Decimation In Time(DIT) and Decimation In Frequency(DIF) algorithms,and DIF algorithm is selected.A simplification of the complex multiplication is performed by an improved algorithm,and then a pipelined Butterfly Processing Element(BPE) is described accordingly.Finally,a VLSI implementation of 64-point radix-2 DIF FFT processor is carried out with a 0.13 μm 1.08V CMOS technology.Synthesis results show the designed FFT processor can operate at 200 MHz,the estimated area and power consumption are only about 2.9mm2 and 15mW,respectively.The proposed fully pipelined FFT processor can be suitably applied in WALN,DVB-T,ADSL and other OFDM-based multicarrier systems.