Studies on Delay Overheads of Power-constrained Non-scan BIST Methods for RTL Data Paths
Dafang Zhang · Computing Technology and Automation · 2006
The methodologies of design for testability(DFT) are widely realized in the digital circuits test.The idea of these techniques is that by adding some test logic the test complexity is reduced drastically.However,after adding the test logic,the delay of the critical path is increased.Therefore,the performance of the DFTed circuits is degraded.In particular,the increased delay may cause delay faults.paper [1] proposed two power-constrained non-scan BIST methods for register transfer level(RTL) data paths.These two methods can achieve shorter test application time and lower hardware overhead compared with the previous methods.This paper studies on the delay overheads of these methods.Experimental results show that we can obtain the same test application time and hardware overhead with a little high delay overhead of the power-constrained non-scan BIST methods for RTL data paths.