Area-efficient VLSI Architecture for Reed-solomon Decoder Based on a Time-domain Algorithm
Zhan-Cai Li · Journal of Chinese Computer Systems · 2008
In this paper,the known decoding procedure for Reed-Solomon(RS)code is analyzed in the way of vector operations that are suitable for VLSI implementation and pipelining.Then,a new area-efficient architecture for RS decoder is proposed.By pipelining,reusing computation unit,folding and sharing circuit,the proposed architecture can improve the reuse rate of the main computation unit for the decoder,decrease the hardware complexity,delete the redundancy circuit and reduce the circuit area.The results show that the total number of gates of the proposed RS(204,188)decoder is about 27,000 gates,which is about 39% smaller than the same kind of conventional ones.It has been integrated in a channel demodulation chip for HDTV and the chip has been tested successfully in practice.