Study on Instruction Scheduling of LU Decomposition on Many-core Architecture Simulator
Xiaochun Ye · Jisuanji fangzhen · 2011
With the development of the technology of integrated circuit,many-core architecture has become the research focus.The task level parallelism improves the performance of applications on many-core architecture.However,the instruction level parallelism is still the important issue that computer architectures designer must handle.The float efficiency and speedup were formalized and the necessity of instruction level scheduling was verified.The pipeline in the core was analyzed in details and the general problems of pipeline were pointed out.The instruction scheduling and software pipeline method were proposed.For the LU decomposition in Splash2,with the hardware support,the method on Scratched Pad Memory was simulated.The experiments show that the speedup can achieve 4 when the matrix is 512×512 and the number of threads is 64.