BIST for SRAM in PCB Level
Tan Enmin · Journal of Guilin University of Electronic Technology · 2004
SRAM is widely used in digital system.In order to maintain its reliability,a BIST structure in PCB level is presented.The fault models in SRAM are discussed first,and then March C-SOF algorithm is selected in the design.It has 100% fault coverage for SAFs,SOFs,TFs,AFs and inter-CFs.Optimized the word-oriented March C-SOF algorithm and added Del element,the algorithm can be used to deal with the intra-CFs and DRFs.A BIST controller,which is realized by using a FPGA,is presented in the last sector of the paper.The test system meets the need for testability in the condition of little additional cost.