Estimating and Optimization of Delay in CMOS Digital Circuit based on Logic Efficacy Model
Sun Xian-long · Microprocessors · 2010
Delay is an important parameter that affects the speed of CMOS digital circuit.This paper introduces modeling of logic efficacy model,estimating delay time,finding the source,deciding the method of decreasing delay,and selecting stages,type of logic gates and size of MOS transistor,finally optimizing logic and circuits.