Hierarchical Netlist Extraction in VLSI layout Verification
Cec Huada · China Integrated Circuit · 2007
In this paper, a new algorithm of hierarchical netlist extraction is proposed. It is based on the data structure of Inverse Layout Tree(ILT). The algorithm builds the hierarchical relations of all geometries among cells in different levels and records connect information through a graph container based on scan line method. By using this algorithm, the original layout hierarchy could be well kept and the extracted netlist has the same hierarchical information as the layout. The method has high efficiency and is successfully used in Zeni Hierarchical Layout Verification tools.