Testing fault in CMOS SRAM circuit based on current signal
Fei Chen · Transducer and Microsystem Technologies · 2008
Aiming at the technology of very deep sub-micron (VDSM) , the method which combines delta-IDDQ and IDDT to test CMOS SRAM is proposed, and the 0-1 arithmetic for the method is improved. The improved 0-1 arithmetic compared to traditional March arithmetic obviously reduces spending of testing. A sample diagnosis of memory circuit which has four cells reaches 100% fault coverage while tests bridge fault,open fault and coupling fault. The test results certify that the new method has high fault coverage, and can diagnose some fault which traditional logic testing difficultly diagnose.