MOSI: A SMT Microarchitecture Based on VLIW Processors
Wan Jiang · Chinese Journal of Computers · 2006
Simultaneous Multi-Threading(SMT) technique has become the hot spot in architecture research because it can effectively improve processors' throughput with relative smaller cost.On the other hand,Very Long Instruction Word(VLIW) is popular in high performance processor design currently.Obviously,applying SMT technique to VLIW processors is profitable,but the remarkable characteristics of these processors,such as lack of hardware dynamic schedule mechanism,make it difficult to implement.This paper presents a SMT microarchitecture based on VLIW processors,named MOSI(MultiOp Splitting Issue).MOSI dynamically issues instructions in the same MultiOp,and introduces write-back buffer that writes results into registers according to the supposed order of compiler,so it tackles the crucial problem in SMT technique with minimal cost.This paper describes the write-back buffer's detail structure and run-time algorithm,and then shows the hardware models of single thread and overall processor.In the end,the organization of Caches and the preferable thread count(hardware supported) are discussed.The experimental result shows that the dual thread processor based on MOSI microarchitecture improves the total throughput by 40%.