Transaction Level Modeling with SystemC2.0
Mingye Liu, Asic Insititute · Jisuanji gongcheng · 2004
Using SystemC2.0, this paper discusses the methodology of transaction level modeling in conjection with AMBA on-chip bus models and with the algorithm of lossless wavelet lifting scheme in JPEG2000, gives an example of transaction level modeling. It is proved that this methodology is very helpful for system-on-chip(SoC) design. It also gives the general methods and necessary steps of creating a SystemC transaction -level processor model from an existing instruction-set simulator.