Novel Efficient VLSI Architecture for Discrete Wavelet Transforms
Jianhua Hou · Jisuanji gongcheng · 2005
A Novel area and power efficient VLSI architecture for 5-3 and 9-7 wavelet transform, based on the lifting schemes, is proposed.Where, the time division multiplexing and embedded pipeline techniques are adopted to optimize the design of the architectures. It reducessignificantly the numbers of the multipliers, adders and registers required, and the amount of memory access, leading to decrease efficiently theoccupied area and power consumption of the design. The system is designed to generate one output in every clock cycle, the detail component andthe approximation of the input signal are available alternately. The presented architecture is simple, regular , scalable, and suited for VLSIimplementation.