4-Core Parallel Architecture for 5/3 Lifting-Based DWT
Yin Hui · 2012
2-D 5/3 lifting-based discrete wavelet transform(DWT) algorithm and its circuit architecture were studied.To reduce the transpose memory and improve the speed,a pipeline optimized architecture of four-core parallel processing was proposed,in which two row processors scanned the raw data from both odd and even rows in parallel,to perform 1-D DWT in row direction,and two column processors scanned in parallel both high and low frequency coefficients directly,to perform 1-D DWT in column direction,without any transpose memory.Each processor was optimized by specially designed pipeline to reduce the critical path.Implemented in Xilinx's Sparten6-xc6slx150t,the new architecture achieved a clock frequency up to 261 MHz,and it required only 2N transpose memory to transform N×N size image.