Clock Tree Synthesis in ASIC Backend Design
HE Ming-hua · Modern Electronics Technique · 2011
Clock tree synthesis is an important part in integrated circuit design nowadays.Therefore,the method of timing-driven placement and limitation of placement density are adopted to achieve good layout effect during the layout design of FFT processor chip.The optimal method of clock tree automatic synthesis and manually modification are employed to reduce clock skew.The strategy of specifying clock tree constraint file,chosing the buffer and modifying clock tree is put forward.The clock tree synthesis of FFT processor chip is completed and the design meets the requirements of design.