VLSI Architecture for1-D Discrete Wavelet Transform
Yigang He · Microelectronics & Computer · 2004
This paper presents a VLSI implementation of discrete wavelet transform(DWT).It comprises of four basic unit:input delay,filter,register bank,and control unit.The proposed architecture adopt recursive pyramid algorithm(RPA)instead of the classical pyramid algorithm(PA),only one low-pass filter and high-pass filter are required to compute all levels.In addition,the architecture is combined with the short-length FIR filter algorithms to reduce the number of multiplications and additions.At the same time,the number of registers in the architecture is minimized by the use of lifetime analysis technique and forward-backward register allocation scheme(FBRA).