Simulated annealing algorithm applied in low power BIST scheme
Asic System · 2002
An approach to approximately optimal group test vectors in a certain length of test patterns is proposed to decrease the number of test vectors based on simulated annealing algorithm. By the scheme of reseeding, this approach makes linear feedback shift register (LFSR) generate optimized groups of vectors, so as to reduce the power consumption without any loss of fault coverage. The experiment result shows that more than 70% power consumption can be reduced while keeping the fault coverage invariable. In addition, the test time is greatly shortened with decreased number of test vectors, which is important in real time device.