Parallel VLSI architecture design for 2D-Discrete 5/3 wavelet transform
Xiaojuan Wu · Radio and communications technology · 2006
A parallel pipelined architecture that performs the forward and inverse 5/3 discrete wavelet transform (DWT) is proposed by using a lifting-based scheme. The architecture uses the row and column filters for filtering simultaneously. The whole architecture is optimized in the pipeline design way to increase the transform speed, and achieve higher hardware utilization. Finally, the architecture has been implemented in behavioral Verilog HDL. The architecture can be used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications,and can be applied to 9/7 discrete wavelet transform.