Transactional Memory Architecture Supporting I/O Operations within Transactions
Depei Qian · Dianzi xuebao · 2009
To support I/O operations inside transactions,this paper proposes a hardware transactional memory system architecture based on multi-core processor and current cache coherent mechanisms,It supports transactions by adding transactional buffer and related hardware and software.I/O operations within transactions are implemented by partial commit based on commit-lock,and blocking / waking-up of transactional threads.This solution solves or avoids the problems that I/O operations within transactions faced,including rollback,transaction migration and transactional buffer overflow.The system has been implemented by simulation.Its performance is evaluated by 5 benchmark applications.Simulation results show that the transactional programs executed in our system outperformed traditional lock-based programs.