An Approach of Design for High-Speed Floating-point Adder
Liu Cong · Microelectronics & Computer · 2003
High-Speed Floating-point Adder is a critical part in the coprocessor,which is attached to the computing basis of floating-point instructions.The paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading-zero logic circuits,consid-ering algorithm and construction of logic circuits.The method improves the performance such as higher speed and lower pow-er.It has been embedded in the coprocessor,successfully pass-ing the product test.