High Level Array Processors Synthesis of Digital Signal Processing
Cad La · Dianzi xuebao · 1993
A high level architectural synthesis procedure on DSP is given in the paper. An architecture of Systolic Array Processors is implemented in the DSP synthesis system. Starting from FDDL(1) behavorial description of DSP algorithms, a list of procedures as parsing, partitioning, DDG (Data Dependency Graph) generation, space projection scheduling, retiming, data-path allocation are needed to generate the systolic processors array of an application-specific DSP algorithm. The synthesis algorithms and optimization strategies in each design stage are also studied, and some results are illustrated.