Design of high-performance 32-bit floating-point multipliers for ASIC
Han Yue-qiu · Systems engineering and electronics · 2004
A design of high-performance 32-bit floating-point multipliers for ASIC is presented. By using a structure of 4:2 column compression trees with the modified Booth encoding, the speed of the multipliers is improved and the power of the system is reduced. Furthermore, due to a more regular structure adopted, it is easy for VLSI realization of the multipliers. The whole design is described in Verilog HDL at structurelevel, and synthesized using the TSMC 0.25 standard cell library. With the technology of three-stage pipeline, 28.98ns is needed to complete a 32-bit floating-point multiplication, and the frequency of the system can reach 103.52MHz.