Research on the Performance of the Parallel Accelerating Board Based on the SHARC DSP Chip
Jie Gao · Jisuanji gongcheng · 2003
Firstly, the paper analyses the structure and the working principle of the parallel accelerating board based on the SHARC DSP chip in detail. Secondly, the performance of the board is researched, which takes implementation of parallel algorithms for the famous mandelbrot Set and a non-linear transient heat transfer equation as examples. In the end, the efficiency of the parallel algorithms are tested respectively on the several computers with multibus or ISA, or PCI standard industrial bus, which are all composed of the boards. The result shows the parallel accelerating board can be plugged into a lot of computers, which have stable performance, powerful function, convenient usage and fast computation speed. It will has widespread prospect.