VLSI Design and Implementation of a High-speed MPEG2 IQ Unit
WU Yuyan · Jisuanji gongcheng · 2004
In this paper, a VLSI design and implementation of a high-speed MPEG2 IQ unit is described. It utilizes a high-speed Wallace-booth multiplier to improve the circuit operation speed. At a frequency of 75 MHz, the unit is synthesized by 0.35μm CMOS cell library with Synopsys software. It costs 3500 gates and the delay of critical path is 10.3ns. The IQ can be used in HDTV video decoder.