FPGA Implementation of a 64-bit Divider Based on Abacus Algorithm
Fa Wang · Science Technology and Engineering · 2014
With the rapid development of digital signal processing,more and more attention is paid to divider in the development of computer and chip technology. Adhering to the principles of operational model in the Ancient Mathematics,on the FPGA a high-performance 64-bit divider is designed which significantly reduces the delay of critical path by correspondinga rowin the abacus to four binary numbers and utilizing abacus division to produce four binary quotient. By component instantiation,abacus division formulas,which is mapped to five modules that are Quotient-Digit,Initial-Quotient,Subtract-Quotient,Hit-Back and Add-Quotient,controls state machine to make calculations on the principle of abacus division. By the simulation of ISE and the verification of Xilinx Virtex-2P,the average computing cycle for a 64-bit abacus divider that can be provided with the maximum working frequency of 184 MHz is only 0. 347 8 μs. It is suitable for the higher requirements for computing power and speed of the FPGA design applications.