High-speed low-power clock network design for NoC
Gang Liu · Journal of Xidian University · 2013
In order to achieve a high-speed low-power NoC(Network-on-chip) clock network,considering the Mesh NoC,a waterfall clock network based on the capacitively-driven low-swing transceiver in which we replace traditional MOS capacitance by metal-insulator-metal(MIM) capacitance as the driven capacitance and receiver coupling capacitance is proposed.These structures are simulated by 0.13 μm CMOS technology with Spectre simulators.Results show that the proposed clock network can reach a high frequency up to 5 GHz,compared with traditional networks,and this network allows up to 49% power saving and 55% delay reduction.At the same time,this network has a better noise suppression ability.