Power Optimization of Technology-dependent Circuits Based on Static Logic Implications
Zhe Zhou · Microelectronics & Computer · 2005
This paper presents a method to the problem of optimizing technology mapped combinational circuits for low power. First, the nodes are sorted according to their switching activity, they are considered one at a time, and static logic implication is used to identify direct and indirect logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit; this may help in eliminating high-power dissipating nodes, thus reducing the total switching activity and power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power.