An IEEE 1149.1 Compliant DFT (Design For Test) Architecture
Ying Zhi · Microelectronics & Computer · 2003
The IEEE Std. 1149.1 (JTAG),which supports Boundary;Scan design of a chip,provides a standard Test;Access Port (TAP). And now,JTAG is almost an essential overhead for every chip in boards. The paper proposes a JTAG customizing approach to managing all the DFT logic,for flexibility and less DFT overhead.