IP Core Design for Varied Parameters RS Decoder
Gaohui Liu · 2005
A variable RS decoder with IP core circuit is designed in this paper,and the circuit can decode RS(15,5),RS(15,7),RS(15,9) and RS(15,11).BM iterative decode algorithm is availed in the decoder,and the circuit has been imporoved to decode complicated RS code.Moreover,there are many shareable modules used in the decoder,and it can reduce the circuit scale.The decoder is described by Verilog Hardware Description Language,and verified in FPGA.The paper shows the hardware verification result in logic analyzer.