Signal integrity design on interconnection of DDR3 system
Chao Zhang · Jisuanji gongcheng yu sheji · 2013
In order to solve the signal integrity and timing problems in the interconnection of DDR3 system,a system-level simulation analysis and optimal design of the interconnection for a Loongson 3A CPU and four DDR3 SDRAM chips are described.First,the structure of IBIS(Input/Output Buffer Information Specification) model is analyzed,and a method for verifying the accuracy of IBIS model quickly is described.Then the DDR3 differential clock circuit is simulated and a method to control common noise of differential circuit is verified.Last,the Fly-By topology used on the interconnection of CPU and Multi-chips is simulated and both the timing and signal quality are analyzed.The simulation results achieved the expected goals.