Research of NCL circuits parallel processing architecture
Zibin Dai · Computer Engineering and Applications Journal · 2010
This paper proposes a framework of NCL circuits parallel processing for reducing the NCL data wave time.After the two dual-rail data waves through the parallel circuits,the next null data has been calculated,so,the data to data cycle time has been shortened.Taking the 4×4 multiplier for example,the circuits have been fabricated in 0.18 μm CMOS process.In the case of non-pipelining module,TDD has reduced 32.9% and in the case of 2 stage pipelining module,TDD has reduced 33.2%.