The development and application of full custom EDA techniques in YHFT-DX
Zhigang Fu · Journal of National University of Defense Technology · 2013
Several full custom EDA techniques were developed during the design of YHFT-DX processor.Hierarchical functional model extraction,which can convert a transistor-level netlist into an equivalent RTL netlist,were developed for the functional verification of full custom circuits.Hybrid timing analysis was researched for the transistor-level timing analysis.10x run-time improvements were achieved by the multi-thread parallel optimization.A measurement was developed to get delays from the simulation waveforms,which improves the efficiency of simulation results analysis.Two signal integrity verification tools,PNVisual and NoiseSpy,were developed for IR-Drop and noise analysis of full custom circuits.These techniques have been widely used in the design of YHFT-DX,which greatly improves the efficiency and quality of full custom design.